View ML145156RP_6807974.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

www.lansdale.com page 1 of 35 issue a ml145151 ml145152 ml145155 ml145156 ml145157 ml145158 pll frequency synthesizer family - cmos the devices described in this document are typically used as low?ower, phase?ocked loop frequency synthesizers. when combined with an external low?ass filter and voltage?ontrolled oscillator, these devices can provide all the remaining functions for a pll frequency synthesizer operating up to the device's frequency limit. for higher vco frequency operation, a down mixer or a prescaler can be used between the vco and the synthesizer ic. these frequency synthesizer chips can be found in the following and other applications: catv tv tuning am/fm radios scanning receivers two?ay radios amateur radio contents page device detail sheets ml145151 parallel?nput, single?odulus ........................................................................................ ...2 ml145152 parallel?nput, dual?odulus.......................................................................................... ....5 ml145155 serial?nput, single?odulus .......................................................................................... ....9 ml145156 serial?nput, dual?odulus............................................................................................ ...13 ml145157 serial?nput, single?odulus .......................................................................................... ..17 ml145158 serial?nput, dual?odulus............................................................................................ ...20 family characteristics maximum ratings................................................................................................................ ..................23 dc electrical characteristics.................................................................................................. ...............23 ac electrical characteristics .................................................................................................. ...............25 timing requirements............................................................................................................ .................26 frequency characteristics ...................................................................................................... ................27 phase detector/lock detector output waveforms................................................................................27 design considerations phase?ocked loop ?low?ass filter design ....................................................................................2 8 crystal oscillator considerations .............................................................................................. ............29 dual?odulus prescaling........................................................................................................ ..............30 r osc control logic n a p/p + 1 vco output frequency external components
www.lansdale.com page 2 of 35 issue a ml145151 parallel-input pll frequency synthesizer interfaces with singlemodulus prescalers legacy device: motorola/freescale mc145151 the ml145151 is programmed by 14 parallel?nput data lines for the n counter and three input lines for the r counter. the device features consist of a reference oscillator, selec- table?eference divider, digital?hase detector, and 14?it programmable divide?y? counter. ? operating temperature range: t a = ?40 to 85? ? low power consumption through use of cmos technology ? 3.0 to 9.0 v supply range ? on?or off?hip reference oscillator operation ? lock detect signal ? n counter output available ? single modulus/parallel programming ? 8 user?electable r values: 8, 128, 256, 512, 1024, 2048, 2410, 8192 ? n range = 3 to 16383 ? ?inearized?digital phase detector enhances transfer function linearity ? two error signal options: single?nded (three?tate) or double?nded ? chip complexity: 8000 fets or 2000 equivalent gates p dip 28 = yp plastic dip case 710 so 28w = -6p sog package case 751f 1 28 1 28 note : lansdale lead free ( p b ) product, as it becomes available, will be identified by a part number prefix change from ml to ml e . cross reference/ordering information motorola p dip 28 mc145151p2 ml145151yp s o 28w mc145151dw2 ml145151-6p lan s dale package 5 4 3 2 1 10 9 8 7 6 11 12 1 3 14 20 21 22 2 3 24 25 26 19 27 28 18 17 16 15 ra2 pd o u t v dd v ss f in n0 r ra0 n 3 n2 n1 ra1 v f v n10 n11 o s c o u t o s c in ld n5 n6 n7 n4 n9 n12 n1 3 n8 t/r pin assignment
www.lansdale.com page 3 of 35 issue a lan s dale s emiconductor, inc. ml145151 14 x 8 rom reference decoder 14?it n counter v ml145151 block diagram r 14?it r counter tran s mit off s et adder pha s e detector b pha s e detector a lock detect ld pd o u t ra2 f in v dd o s c in o s c o u t t/r 14 14 f v n1 3 n11 n9 n7 n6 n4 n2 n0 note: n0 ?n1 3 inp u t s a nd inp u t s ra0, ra1, a nd ra2 h a ve p u ll u p re s i s tor s th a t a re not s hown. ra0 ra1 pin descriptions input pins f in frequency input (pin 1) input to the ? portion of the synthesizer. f in is typically derived from loop v co and is ac coupled into the device. for larger amplitude signals (standard cmos logic levels) dc coupling may be used. ra0 ?ra2 reference address inputs (pins 5, 6, 7) these three inputs establish a code defining one of eight possible divide values for the total reference divider, as defined by the table below. pull?p resistors ensure that inputs left open remain at a logic 1 and require only a spst switch to alter data to the zero state. n0 ?n11 n counter programming inputs (pins 11 ?20, 22 ?25) these inputs provide the data that is preset into the n counter when it reaches the count of zero. n0 is the least sig- nificant and n13 is the most significant. pull?p resistors en- sure that inputs left open remain at a logic 1 and require only an spst switch to alter data to the zero state. t/r transmit/receive offset adder input (pin 21) this input controls the offset added to the data provided at the n inputs. this is normally used for offsetting the v co fre- quency by an amount equal to the if frequency of the trans- ceiver. this offset is fixed at 856 when t/r is low and gives no offset when t/r is high. a pull?p resistor ensures that no connection will appear as a logic 1 causing no offset addition. osc in , osc out reference oscillator input/output (pins 27, 26) these pins form an on?hip reference oscillator when con- nected to terminals of an external parallel resonant crystal. frequency setting capacitors of appropriate value must be con- nected from osc in to ground and osc out to ground. osc in may also serve as the input for an externally generated refer- ence signal. this signal is typically ac coupled to osc in , but for larger amplitude signals (standard cmos logic levels) dc coupling may also be used. in the external reference mode, no connection is required to osc out . output pins pdout phase detector a output (pin 4) three?tate output of phase detector for use as loop?rror signal. double?nded outputs are also available for this pur- pose (see v and r). frequency f v > f r or f v leading: negative pulses frequency f v < f r or f v lagging: positive pulses frequency f v = f r and phase coincidence: high?mped- ance state reference address code total divide ra2 ra1 ra0 di v id e value 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 8 128 256 512 1024 2048 2410 8192
www.lansdale.com page 4 of 35 issue a r, v phase detector b outputs (pins 8, 9) these phase detector outputs can be combined externally for a loop?rror signal. a single?nded output is also available for this purpose (see pd out ). if frequency f v is greater than f r or if the phase of f v is leading, then error information is provided by v pulsing low. r remains essentially high. if the frequency f v is less than f r or if the phase of f v is lagging, then error information is provided by r pulsing low. v remains essentially high. if the frequency of f v = f r and both are in phase, then both v and r remain high except for a small minimum time peri- od when both pulse low in phase. f v n counter output (pin 10) this is the buffered output of the n counter that is inter- nally connected to the phase detector input. with this output available, the n counter can be used independently. ld lock detector output (pin 28) essentially a high level when loop is locked (f r , f v of same phase and frequency). pulses low when loop is out of lock. power supply v dd positive power supply (pin 3) the positive power supply potential. this pin may range from + 3 to + 9 v with respect to v ss . v ss negative power supply (pin 2) the most negative supply potential. this pin is usually- ground. lan s dale s emiconductor, inc. ml145151 typical applications figure 1. 5 mhz to 5.5 mhz local oscillator channel spacing = 1 khz 0 1 1 1 0 0 0 1 0 0 0 = 5 mhz 1 0 1 0 1 1 1 1 1 0 0 = 5.5 mhz 5 ?5.5 mhz voltage controlled o s cillator nc nc pd o u t ra0 ra1 ra2 n1 3 n0 n1 n2 n 3 n4 n5 n6 n7 n8 n9 n10 n11 n12 ml145151 f in o s c o u t o s c in 2.048 mhz figure 2. synthesizer for land mobile radio uhf bands note s : 1. f r = 4.1667 khz; r = 2410; 21.4 mhz low s ide injection d u ring receive. 2. freq u ency v a l u e s s hown a re for the 440 ?470 mhz b a nd. s imil a r implement a tion a pplie s to the 406 ?440 mhz b a nd. for 470 ?512 mhz, con s ider reference o s cill a tor freq u ency x9 for mixer injection s ign a l (90. 3 750 mhz). 60.2500 mhz ? ? ? choice of detector error s ignal s lock detect s ignal t: 1 3 .08 33 ?18.08 33 mhz r: 9.5167 ?14.5167 mhz t: 7 3 . 3333 ?78. 3333 mhz r: 69.7667 ?74.7667 mhz x6 vco loop filter down mixer x6 t/r v ss v dd channel programming n = 2284 to 3 484 tran s mit (add s 856 to n value) receive ref. o s c. 10.0417 mhz (on?hip o s c. optional) ? ? ? f v ld ra0 ra1 ra2 o s c in o s c o u t ml145151 + v tran s mit: 440.0 ?470.0 mhz receive: 418.6 ?448.6 mhz (25 khz s tep s ) pd o u t r f v f in ml145151 data sheet continued on page 23
www.lansdale.com page 5 of 35 issue a ml145152 parallel-input pll frequency synthesizer interfaces with dualmodulus prescalers legacy device: motorola/freescale mc145152 the ml145152 is programmed by sixteen parallel inputs for the n and a counters and three input lines for the r counter. the device features consist of a reference oscillator, selectable?eference divider, two?utput phase detector, 10?it programmable divide?y? counter, and 6?it pro- grammable a counter. ? operating temperature range: t a = ?40 to 85? ? low power consumption through use of cmos technology ? 3.0 to 9.0 v supply range ? on?or off?hip reference oscillator operation ? lock detect signal ? dual modulus/parallel programming ? 8 user?electable r values: 8, 64, 128, 256, 512, 1024, 1160, 2048 ? n range = 3 to 1023, a range = 0 to 63 ? chip complexity: 8000 fets or 2000 equivalent gates ? see application note an980 p dip 28 = yp pla s tic dip ca s e 710 so 28w = -6p s og package ca s e 751f 1 28 1 28 note : lansdale lead free ( p b ) product, as it becomes available, will be identified by a part number prefix change from ml to ml e . cross reference/ordering information motorola p dip 28 mc145152p2 ml145152yp s o 28w mc145152dw2 ml145152-6p lan s dale package 5 4 3 2 1 10 9 8 7 6 11 12 1 3 14 20 21 22 2 3 24 25 26 19 27 28 18 17 16 15 r ra0 v dd v ss f in n0 v ra1 n 3 n2 n1 ra2 mc a5 a 3 a4 o s c o u t o s c in ld n5 n6 n7 n4 n9 a2 a0 n8 a1 pin assignment
www.lansdale.com page 6 of 35 issue a lan s dale s emiconductor, inc. ml145152 12 x 8 rom reference decoder v ml145152 block diagram r 12?it r counter pha s e detector lock detect ld f in o s c in o s c o u t 12 n0 n2 n4 n5 n7 n9 note: n0 ?n9, a0 ?a5, a nd ra0 ?ra2 h a ve p u ll u p re s i s tor s th a t a re not s hown. 10?it n counter control logic mc 6?it a counter a5 a 3 a2 a0 ra2 ra0 ra1 pin descriptions input pins f in frequency input (pin 1) input to the positive edge triggered n and a counters. f in is typically derived from a dual?odulus prescaler and is ac coupled into the device. for larger amplitude signals (stan- dard cmos logic levels) dc coupling may be used. ra0, ra1, ra2 reference address inputs (pins 4, 5, 6) these three inputs establish a code defining one of eight possible divide values for the total reference divider. the total reference divide values are as follows: n0 ?n9 n counter programming inputs (pins 11 ?20) the n inputs provide the data that is preset into the n counter when it reaches the count of 0. n0 is the least signifi- cant digit and n9 is the most significant. pull?p resistors en- sure that inputs left open remain at a logic 1 and require only a spst switch to alter data to the zero state. a0 ?a5 a counter programming inputs(pins 23, 21, 22, 24, 25, 10) the a inputs define the number of clock cycles of f in that require a logic 0 on the mc output (see dual?odulus pres- caling section). the a inputs all have internal pull?p resis- tors that ensure that inputs left open will remain at a logic 1. osc in , osc out reference oscillator input/output (pins 27, 26) these pins form an on?hip reference oscillator when con- nected to terminals of an external parallel resonant crystal. frequency setting capacitors of appropriate value must be con- nected from osc in to ground and osc out to ground. osc in may also serve as the input for an externally generated refer- ence signal. this signal is typically ac coupled to osc in , but for larger amplitude signals (standard cmos logic levels) dc coupling may also be used. in the external reference mode, no connection is required to osc out . output pins r, v phase detector b outputs (pins 7, 8) these phase detector outputs can be combined externally for a loop?rror signal. if the frequency f v is greater than f r or if the phase of f v is leading, then error information is provided by v pulsing low. r remains essentially high. if the frequency f v is less than f r or if the phase of f v is lagging, then error information is provided by r pulsing low. v remains essentially high. if the frequency of f v = f r and both are in phase, then both v and r remain high except for a small minimum time peri- od when both pulse low in phase. mc dual?odulus prescale control output (pin 9) signal generated by the on?hip control logic circuitry for controlling an external dual?odulus prescaler. the mc level will be low at the beginning of a count cycle and will remain low until the a counter has counted down from its pro- grammed value. at this time, mc goes high and remains high until the n counter has counted the rest of the way down from its programmed value (n ?a additional counts since both n and a are counting down during the first portion of the cycle). mc is then set back low, the counters preset to reference address code total divide ra2 ra1 ra0 di v id e value 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 8 64 128 256 512 1024 1160 2048
www.lansdale.com page 7 of 35 issue a their respective programmed values, and the above sequence repeated. this provides for a total programmable divide value (nt)=n?+a where p and p + 1 represent the dual?odulus prescaler divide values respectively for high and low mc lev- els, n the number programmed into the n counter, and a the number programmed into the a counter. ld lock detector output (pin 28) essentially a high level when loop is locked (f r , f v of same phase and frequency). pulses low when loop is out of lock. power supply vdd positive power supply (pin 3) the positive power supply potential. this pin may range from + 3 to + 9 v with respect to v ss . v ss negative power supply (pin 2) the most negative supply potential. this pin is usually- ground. lan s dale s emiconductor, inc. ml145152 typical applications figure 1. synthesizer for land mobile radio vhf bands note s : 1. off?hip o s cill a tor option a l. 2. the r a nd v o u tp u t s a re fed to a n extern a l combiner/loop filter. s ee the ph as e?ocked loop ?low? ass filter de s ign p a ge for a ddition a l inform a tion. the r a nd v o u tp u t s s wing r a il?o? a il. therefore, the us er s ho u ld be c a ref u l not to exceed the common mode inp u t r a nge of the op a mp us ed in the combiner/loop filter. lock detect s ignal 10.24 mhz note 1 r1 mc33171 note 2 + 150 ?175 mhz 5 khz s tep s ml12017 64/65 pre s caler ml145152 mc ld a0 a5 n9 o s c in v dd v ss o s c o u t ra2 ra1 r v f in vco ra0 n0 + v r1 r2 c r2 c ? ? ? no connect s channel programming
www.lansdale.com page 8 of 35 issue a lan s dale s emiconductor, inc. ml145152 figure 2. 666?hannel, computer?ontrolled, mobile radiotelephone synthesizer for 800 mhz cellular radio systems lock detect s ignal r1 + receiver fir s t l.o. 825.0 3 0 844.980 mhz ( 3 0 khz s tep s ) ml12017 64/65 pre s caler note 6 ml145152 note 5 mc ld a0 a5 n9 o s c in v dd v ss o s c o u t ra2 ra1 r v f in vco ra0 n0 + v r1 r2 c r2 c ? ? ? no connect s channel programming note s : 1. receiver 1 s t i.f. = 45 mhz, low s ide injection; receiver 2nd i.f. = 11.7 mhz, low s ide injection. 2. d u plex oper a tion with 45 mhz receiver/tr a n s mit s ep a r a tion. 3 .f r = 7.5 khz; r = 2048. 4. n tot a l = n 64 + a = 27501 to 28166; n = 429 to 440; a = 0 to 6 3 . 5. ml145158 m a y be us ed where s eri a l d a t a entry i s de s ired. 6. high freq u ency pre s c a ler s m a y be us ed for higher freq u ency vco a nd f ref implement a tion s . 7. the r a nd v o u tp u t s a re fed to a n extern a l combiner/loop filter. s ee the ph as e?ocked loop ?low? ass filter de s ign p a ge for a ddition a l inform a tion. the r a nd v o u tp u t s s wing r a il?o? a il. therefore, the us er s ho u ld be c a ref u l not to exceed the common mode inp u t r a nge of the op a mp us ed in the combiner/loop filter. ref. o s c. 15. 3 60 mhz (on?hip o s c. optional) x2 x4 note 6 x4 note 6 tran s mitter modulation tran s mitter s ignal 825.0 3 0 844.980 mhz ( 3 0 khz s tep s ) receiver 2nd l.o. 3 0.720 mhz note 7 ml145152 data sheet continued on page 23
www.lansdale.com page 9 of 35 issue a ml145155 serial?nput pll frequency synthesizer interfaces with singlemodulus prescalers legacy device: motorola/freescale mc145155-2 the ml145155 is programmed by a clocked, serial input, 16?it data stream. the device features consist of a reference oscillator, selectable?eference divider, digital?hase detector, 14?it programmable divide?y? counter, and the necessary shift register and latch circuitry for accepting serial input data. ? operating temperature range: t a = ?40 to 85? ? low power consumption through use of cmos technology ? 3.0 to 9.0 v supply range ? on?or off?hip reference oscillator operation with buffered output ? compatible with the serial peripheral interface (spi) on cmos mcus ? lock detect signal ? two open?rain switch outputs ? 8 user?electable r values: 16, 512, 1024, 2048, 3668, 4096, 6144, 8192 ? single modulus/serial programming ? n range = 3 to 16383 ? ?inearized?digital phase detector enhances transfer function linearity ? two error signal options: single?nded (three?tate) or double?nded ? chip complexity: 6504 fets or 1626 equivalent gates p dip 1 8 = vp plastic dip case 707 s og 20w = -6p sog package case 751d 1 1 8 20 1 cro ss reference/ordering information motorola p dip 1 8 mc145155p2 ml145155vp sog 20w mc145155dw2 ml145155-6p lansdale package note : lansdale lead free ( pb ) product, as it becomes available, will be identified by a part number prefix change from ml to mle . pin a ss ignment s v dd v ra2 ra1 f in ld v ss pd out r ref out osc out osc in ra0 clk data enb sw1 sw2 14 15 16 17 1 8 10 11 12 13 5 4 3 2 1 9 8 7 6 pla s tic dip pd out r v ra2 ra1 f in ld nc v ss v dd 5 4 3 2 1 10 9 8 7 6 14 15 16 17 1 8 19 20 11 12 13 nc ref out osc out osc in ra0 clk data enb sw1 sw2 s og package nc = no connection
www.lansdale.com page 10 of 35 issue a lan s dale s emiconductor, inc. ml145155 14 x 8 rom reference decoder 14?it r counter v r 14?it r counter latch phase detector b phase detector a lock detect ld pd out f in v dd osc in osc out enb 14 14 sw2 sw1 f r f v latch 14?it shift register data 2?it shift register clk 14 ref out ml145155 block diagram ra2 ra0 ra1 pin descriptions input pins f in frequency input (pdip ?pin 9, sog ?pin 10) input to the n portion of the synthesizer. f in is typically derived from loop vco and is ac coupled into the device. for larger amplitude signals (standard cmos logic levels) dc coupling may be used. ra0, ra1, ra2 reference address inputs (pdip ?pins 18, 1, 2; sog pins 20, 1, 2) these three inputs establish a code defining one of eight possible divide values for the total reference divider, as defined by the table below: clk, data shift register clock, serial data inputs (pdip ?pins 10, 11; sog ?pins 11, 12) each low?o?igh transition clocks one bit into the on?hip 16?it shift register. the data input provides programming information for the 14?it n counter and the two switch signals sw1 and sw2. the entry format is as follows: enb latch enable input (pdip ?pin 12, sog ?pin 13) when high (1), enb transfers the contents of the shift reg- ister into the latches, and to the programmable counter inputs, and the switch outputs sw1 and sw2. when low (0), enb inhibits the above action and thus allows changes to be made in the shift register data without affecting the counter program- ming and switch outputs. an on?hip pull?p establishes a continuously high level for enb when no external signal is applied. enb is normally low and is pulsed high to transfer data to the latches. osc in , osc out reference oscillator input/output (pdip ?pins 17, 16; sog ?pins 19, 18) these pins form an on?hip reference oscillator when con- nected to terminals of an external parallel resonant crystal. frequency setting capacitors of appropriate value must be con- nected from osc in to ground and osc out to ground. osc in may also serve as the input for an externally?enerated refer- ence signal. this signal is typically ac coupled to osc in , but for larger amplitude signals (standard cmos logic levels) dc coupling may also be used. in the external reference mode, no connection is required to osc out . reference addre ss code total divide ra2 ra1 ra0 di v id e value 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 16 512 1024 204 8 366 8 4096 6144 8 192 sw2 sw1 ? n msb ? n lsb ? n counter bits last data bit in (bit no. 16) first data bit in (bit no. 1)
www.lansdale.com page 11 of 35 issue a lan s dale s emiconductor, inc. ml145155 ml145155 typical application s fi g ure 1. microproce ss or?ontrolled tv/catv tunin g s y s tem with s erial interface f in 3 led display mc144 8 9 keyboard cmos mpu/mcu enb clk data 1/2 mc145 8 * ml145155 mc120xx prescaler uhf/vhf tuner or catv front end 4.0 mhz v r + * the r and v outputs are fed to an external com b iner/loop filter. see the phase?ocked loop ?low?ass filter design page for additional information. the r and v outputs swing rail?o?ail. therefore, the user should b e careful not to exceed the common mode input range of the op amp used in the com b iner/loop filter. output pins pd out phase detector a output (pdip, sog ?pin 6) three?tate output of phase detector for use as loop error signal. double?nded outputs are also available for this pur- pose (see v and r). frequency f v > f r or f v leading: negative pulses frequency f v < f r or f v lagging: positive pulses frequency f v = f r and phase coincidence: high?mped- ance state r, v phase detector b outputs (pdip, sog ?pins 4, 3) these phase detector outputs can be combined externally for a loop?rror signal. a single?nded output is also available for this purpose (see pd out ). if frequency f v is greater than f r or if the phase of f v is leading, then error information is provided by f v pulsing low. f r remains essentially high. if the frequency f v is less than f r or if the phase of f v is lagging, then error information is provided by f r pulsing low. f v remains essentially high. if the frequency of f v = f r and both are in phase, then both f v and f r remain high except for a small minimum time peri- od when both pulse low in phase. ld lock detector output (pdip ?pin 8, sog ?pin 9) essentially a high level when loop is locked (f r , f v of same phase and frequency). ld pulses low when loop is out of lock. sw1, sw2 band switch outputs (pdip pins 13, 14; sog pins 14, 15) sw1 and sw2 provide latched open?rain outputs corre- sponding to data bits numbers one and two. these outputs can be tied through external resistors to voltages as high as 15 v, independent of the v dd supply voltage. these are typically used for band switch functions. a logic 1 causes the output to assume a high?mpedance state, while a logic 0 causes the out- put to be low. ref out buffered reference oscillator output (pdip, sog pin 15) buffered output of on?hip reference oscillator or externally provided reference?nput signal. power supply vdd positive power supply (pdip, sog ?pin 5) the positive power supply potential. this pin may range from + 3 to + 9 v with respect to v ss . vss negative power supply (pdip, sog ?pin 7) the most negative supply potential. this pin is usually ground.
www.lansdale.com page 12 of 35 issue a fi g ure 2. am/fm radio s ynthe s izer to am/fm oscillators to display ml12019 20 prescaler am osc fm osc f in keyboard cmos mpu/mcu enb clk data 1/2 mc145 8 * ml145155 2.56 mhz v r + * the r and v outputs are fed to an external com b iner/loop filter. see the phase?ocked loop ?low?ass filter design page for additional information. the r and v outputs swing rail?o?ail. therefore, the user should b e careful not to exceed the common mode input range of the op amp used in the com b iner/loop filter. ml145155 lan s dale s emiconductor, inc. ml145155
www.lansdale.com page 13 of 35 issue a ml145156 serial?nput pll frequency synthesizer interfaces with dualmodulus prescalers legacy device: motorola/freescale mc145156-2 the ml145156 is programmed by a clocked, serial input, 19?it data stream. the device features consist of a reference oscillator, selectable?eference divider, digital?hase detector, 10?it programmable divide?y? counter, 7?it program- mable divide?y? counter, and the necessary shift register and latch circuitry for accepting serial input data. ? operating temperature range: t a = ?40 to 85? ? low power consumption through use of cmos technology ? 3.0 to 9.0 v supply range ? on?or off?hip reference oscillator operation with buffered output ? compatible with the serial peripheral interface (spi) on cmos mcus ? lock detect signal ? two open?rain switch outputs ? dual modulus/serial programming ? 8 user?electable r values: 8, 64, 128, 256, 640, 1000, 1024, 2048 ? n range = 3 to 1023, ? range = 0 to 127 ? ?inearized?digital phase detector enhances transfer function linearity ? two error signal options: single?nded (three?tate) or double?nded ? chip complexity: 6504 fets or 1626 equivalent gates 1 20 1 20 p dip 20 = rp plastic dip case 73 8 s og 20w = -6p sog package case 751d cro ss reference/ordering information motorola p dip 20 mc145156p2 ML145156RP sog 20w mc145156dw2 ml145156-6p lansdale package note : lansdale lead free ( pb ) product, as it becomes available, will be identified by a part number prefix change from ml to mle . pin a ss ignment pd out r v ra2 ra1 f in ld mc v ss v dd 5 4 3 2 1 10 9 8 7 6 14 15 16 17 1 8 19 20 11 12 13 test ref out osc out osc in ra0 clk data enb sw1 sw2
www.lansdale.com page 14 of 35 issue a lan s dale s emiconductor, inc. ml145156 12 x 8 rom reference decoder v r 12?it r counter phase detector b phase detector a lock detect ld pd out f in v dd osc in osc out enb 12 10 sw2 sw1 f r f v latch data 2?it shift register clk 10 ref out 10?it shift register 7?it shift register a counter latch n counter latch 7?it a counter 10?it n counter control logic mc 7 7 ml145156 block diagram ra2 ra0 ra1 pin descriptions input pins f in frequency input (pin 10) input to the positive edge triggered n and a counters. f in is typically derived from a dual?odulus prescaler and is ac coupled into the device. for larger amplitude signals (stan- dard cmos logic levels), dc coupling may be used. ra0, ra1, ra2 reference address inputs (pins 20, 1, 2) these three inputs establish a code defining one of eight possible divide values for the total reference divider, as defined by the table below: clk, data shift register clock, serial data inputs (pins 11, 12) each low?o?igh transition clocks one bit into the on?hip 19?it shift register. the data input provides programming in- formation for the 10?it n counter, the 7?it a counter, and the two switch signals sw1 and sw2. the entry format is as follows: enb latch enable input (pin 13) when high (1), enb transfers the contents of the shift reg- ister into the latches, and to the programmable counter inputs, and the switch outputs sw1 and sw2. when low (0), enb inhibits the above action and thus allows changes to be made in the shift register data without affecting the counter program- ming and switch outputs. an on?hip pull?p establishes a continuously high level for enb when no external signal is applied. enb is normally low and is pulsed high to transfer data to the latches. osc in , osc out reference oscillator input/output (pins 19, 18) these pins form an on?hip reference oscillator when con- nected to terminals of an external parallel resonant crystal. frequency setting capacitors of appropriate value must be con- nected from osc in to ground and osc out to ground. osc in may also serve as the input for an externally?enerated refer- ence signal. this signal is typically ac coupled to osc in , but for larger amplitude signals (standard cmos logic levels) dc coupling may also be used. in the external reference mode, no connection is required to osc out . test factory test input (pin 16) used in manufacturing. must be left open or tied to v ss . reference addre ss code total divide ra2 ra1 ra0 di v id e value 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 8 64 12 8 256 640 1000 1024 204 8 sw2 sw1 n msb a lsb n counter bits last data bit in (bit no. 19) first data bit in (bit no. 1) a counter bits n lsb a msb
www.lansdale.com page 15 of 35 issue a ml145156 output pins pdout phase detector a output (pin 6) three?tate output of phase detector for use as loop?rror signal. double?nded outputs are also available for this pur- pose (see v and r ). frequency f v > f r or f v leading: negative pulses frequency f v < f r or f v lagging: positive pulses frequency f v = f r and phase coincidence: high?mped- ance state r, v phase detector b outputs (pins 4, 3) these phase detector outputs can be combined externally for a loop?rror signal. a single?nded output is also available for this purpose (see pd out ). if frequency f v is greater than f r or if the phase of f v is leading, then error information is provided by v pulsing low. r remains essentially high. if the frequency f v is less than f r or if the phase of f v is lagging, then error information is provided by r pulsing low. v remains essentially high. if the frequency of f v = f r and both are in phase, then both v and r remain high except for a small minimum time period when both pulse low in phase. mc dual?odulus prescale control output (pin 8) signal generated by the on?hip control logic circuitry for- controlling an external dual?odulus prescaler. the mc level- will be low at the beginning of a count cycle and will remain- low until the a counter has counted down from its pro- grammed value. at this time, mc goes high and remains high- until the n counter has counted the rest of the way down- from its programmed value (n ?a additional counts since both n and a are counting down during the first portion of the cycle). mc is then set back low, the counters preset to their respective programmed values, and the above sequence repeat- ed. this provides for a total programmable divide value (n t ) = n ?p + a where p and p + 1 represent the dual?odulus prescaler divide values respectively for high and low mc lev- els, n the number programmed into the n counter, and a the number programmed into the a counter. ld lock detector output (pin 9) essentially a high level when loop is locked (f r , f v of same phase and frequency). ld pulses low when loop is out of lock. sw1, sw2 band switch outputs (pins 14, 15) sw1 and sw2 provide latched open?rain outputs corre- sponding to data bits numbers one and two. these outputs can be tied through external resistors to voltages as high as 15 v, independent of the v dd supply voltage. these are typically used for band switch functions. a logic 1 causes the output to assume a high?mpedance state, while a logic 0 causes the out- put to be low. ref out buffered reference oscillator output (pin 17) buffered output of on?hip reference oscillator or externally provided reference?nput signal. power supply v dd positive power supply (pin 5) the positive power supply potential. this pin may range from + 3 to + 9 v with respect to v ss . v ss negative power supply (pin 7) the most negative supply potential. this pin is usually- ground. lan s dale s emiconductor, inc. ml145156
www.lansdale.com page 16 of 35 issue a typical application s fi g ure 1. am/fm radio broadca s t s ynthe s izer sw2 sw1 v r pd out mc f in enb data clk ref out v ss v dd ld ra0 ra1 ra2 osc in osc out notes 1 and 2 optional loop error signal ml12019 20/21 dual modulus prescaler vco am b + + 12 v fm b + + 12 v lock detect signal to display driver (e.g., mc144 8 9) cmos mpu/mcu key board + v 3.2 mhz ml145156 1/2 mc145 8 note 3 + notes: 1. for am: channel spacing = 5 khz, r = 640 (code 100). 2. for fm: channel spacing = 25 khz, r = 12 8 (code 010). 3. the r and v outputs are fed to an external com b iner/loop filter. see the phase?ocked loop ?low?ass filter design page for additional information. the r and v outputs swing rail?o?ail. therefore, the user should b e careful not to exceed the common mode input range of the op amp used in the com b iner/loop filter. fi g ure 2. avionic s navi g ation or communication s ynthe s izer nav = 01 com = 10 channel selection vco lock detect signal to display driver (e.g., mc144 8 9) cmos mpu/mcu + v 3.2 mhz (note 3) ml145156 mc33171 note 5 sw2 sw1 v r pd out mc f in enb data clk ref out v ss v dd ld ra0 ra1 ra2 osc in osc out ml12016 (notes 2 and 4) 40/41 dual modulus prescaler + vco range nav: 97.300 ?107.250 mhz com?: 11 8 .000 ?135.975 mhz com?: 139.400 ?157.375 mhz r/t notes: 1. for nav: f r = 50 khz, r = 64 using 10.7 mhz lowside injection, n total = 1946 ?2145. for com?: f r = 25 khz, r = 12 8 , n total = 4720 ?5439. for com?: f r = 25 khz, r = 12 8 , using 21.4 mhz highside injection, n total = 5576 ?6295. 2. a 32/33 dual modulus approach is provided b y su b stituting an ml12015 for the ml12016. the devices are pin e q uivalent. 3. a 6.4 mhz oscillator crystal can b e used b y selecting r = 12 8 (code 010) for nav and r = 256 (code 011) for com. 4. ml12013 + mc10131 com b ination may also b e used to form the 40/41 prescaler . 5. the r and v outputs are fed to an external com b iner/loop filter. see the phase?ocked loop ?low?ass filter design page for additional information. the r and v outputs swing rail?o?ail. therefore, the user should b e careful not to exceed the common mode input range of the op amp used in the com b iner/loop filter. ml145156 data s heet continued on pa g e 2 3 lan s dale s emiconductor, inc. ml145156 ml145156
www.lansdale.com page 17 of 35 issue a ml145157 serial?nput pll frequency synthesizer interfaces with singlemodulus prescalers legacy device: motorola/freescale mc145157-2 the ml145157 has a fully programmable 14?it reference counter, as well as a fully programmable n counter. the counters are programmed serially through a common data input and latched into the appropriate counter latch, accord- ing to the last data bit (control bit) entered. ? operating temperature range: t a = ?40 to 85? ? low power consumption through use of cmos technology ? 3.0 to 9.0 v supply range ? fully programmable reference and n counters ? r range = 3 to 16383 ? n range = 3 to 16383 ? f v and f r outputs ? lock detect signal ? compatible with the serial peripheral interface (spi) on cmos mcus ? ?inearized?digital phase detector ? single?nded (three?tate) or double?nded phase detector outputs ? chip complexity: 6504 fets or 1626 equivalent gates p dip 16 = ep plastic dip case 64 8 s og 16 = -5p sog package case 751g cro ss reference/ordering information motorola p dip 16 mc145157p2 ml145157ep sog 20w mc145157dw2 ml145157-5p lansdale package 1 16 1 16 note : lansdale lead free ( pb ) product, as it becomes available, will be identified by a part number prefix change from ml to mle . pin a ss ignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 s/r out f r ref out v r clk data enb v dd f v osc out osc in f in ld v ss pd out
www.lansdale.com page 1 8 of 35 issue a lan s dale s emiconductor, inc. ml145157 14?it shift register 14?it n counter v ml145157 block diagram r reference counter latch phase detector b phase detector a lock detect ld pd out f in osc in osc out enb 14 14 14?it shift register data clk 14 ref out n counter latch 14?it r counter 14 s/r out f r f v 1?it control s/r pin descriptions input pins fin frequency input (pin 8) input frequency from vco output. a rising edge signal on this input decrements the n counter. this input has an invert- er biased in the linear region to allow use with ac coupled sig- nals as low as 500 mv p?. for larger amplitude signals (stan- dard cmos logic levels), dc coupling may be used. clk, data shift clock, serial data inputs (pins 9, 10) each low?o?igh transition of the clock shifts one bit of data into the on?hip shift registers. the last data bit entered determines which counter storage latch is activated; a logic 1selects the reference counter latch and a logic 0 selects the n counter latch. the entry format is as follows: enb latch enable input (pin 11) a logic high on this pin latches the data from the shift regis- ter into the reference divider or n latches depending on the control bit. the reference divider latches are activated if the control bit is at a logic high and the n latches are activated if the control bit is at a logic low. a logic low on this pin allows the user to change the data in the shift registers without affect- ing the counters. enb is normally low and is pulsed high to transfer data to the latches. oscin, oscout reference oscillator input/output (pins 1, 2) these pins form an on?hip reference oscillator when con- nected to terminals of an external parallel resonant crystal. frequency setting capacitors of appropriate value must be con- nected from osc in to ground and osc out to ground. osc in may also serve as the input for an externally?enerated refer- ence signal. this signal is typically ac coupled to osc in , but for larger amplitude signals (standard cmos logic levels) dc coupling may also be used. in the external reference mode, no connection is required to osc out . output pins pd out single?nded phase detector a output (pin 5) this single?nded (three?tate) phase detector output pro- duces a loop?rror signal that is used with a loop filter to con- trol a vco. frequency fv > fr or fv leading: negative pulses frequency fv < fr or fv lagging: positive pulses frequency fv = fr and phase coincidence: high?mpedance state r, v double?nded phase detector b outputs (pins 16, 15) these outputs can be combined externally for a loop?rror signal. a single?nded output is also available for this purpose (see pd out ). lsb msb control first data bit into shift register
www.lansdale.com page 19 of 35 issue a ml145157 if frequency f v is greater than f r or if the phase of f v is leading, then error information is provided by v pulsing low. r remains essentially high. if the frequency f v is less than f r or if the phase of fv is lagging, then error information is provided by r pulsing low. v remains essentially high. if the frequency of f v = f r and both are in phase, then both v and r remain high except for a small minimum time peri- od when both pulse low in phase. f r ,f v rcounter output, n counter output (pins 13, 3) buffered, divided reference and f in frequency outputs. the f r and f v outputs are connected internally to the r and n counter outputs respectively, allowing the counters to be used independently, as well as monitoring the phase detector inputs. ld lock detector output (pin 7) this output is essentially at a high level when the loop is locked (f r , f v of same phase and frequency), and pulses low when loop is out of lock. ref out buffered reference oscillator output (pin 14) this output can be used as a second local oscillator, refer- ence oscillator to another frequency synthesizer, or as the sys- tem clock to a microprocessor controller. s/r out shift register output (pin 12) this output can be connected to an external shift register to provide band switching, control information, and counter pro- gramming code checking. power supply v dd positive power supply (pin 4) the positive power supply potential. this pin may range from +3 to +9 v with respect to v ss . v ss negative power supply (pin 6) the most negative supply potential. this pin is usually ground. lan s dale s emiconductor, inc. ml145157
www.lansdale.com page 20 of 35 issue a ml145158 serial?nput pll frequency synthesizer interfaces with dualmodulus prescalers legacy device: motorola/freescale mc145158-2 the ml145158 has a fully programmable 14?it reference counter, as well as fully programmable n and a counters. the counters are programmed serially through a common data input and latched into the appropriate counter latch, according to the last data bit (control bit) entered. ? operating temperature range: t a = ?40 to 85? ? low power consumption through use of cmos technology ? 3.0 to 9.0 v supply range ? fully programmable reference and n counters ? r range = 3 to 16383 ? n range = 3 to 1023 ? dual modulus capability; a range = 0 to 127 ? f v and f r outputs ? lock detect signal ? compatible with the serial peripheral interface (spi) on cmos mcus ? ?inearized?digital phase detector ? single?nded (three?tate) or double?nded phase detector outputs ? chip complexity: 6504 fets or 1626 equivalent gates 1 16 1 16 p dip 16 = ep plastic dip case 64 8 s og 16 = -5p sog package case 751g cro ss reference/ordering information motorola p dip 16 mc14515 8 p2 ml14515 8 ep sog 16 mc14515 8 dw2 ml14515 8 -5p lansdale package note : lansdale lead free ( pb ) product, as it becomes available, will be identified by a part number prefix change from ml to mle . pin a ss ignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 mc f r ref out v r clk data enb v dd f v osc out osc in f in ld v ss pd out
www.lansdale.com page 21 of 35 issue a ml14515 8 lan s dale s emiconductor, inc. pin descriptions input pins f in frequency input (pin 8) input frequency from vco output. a rising edge signal on this input decrements the a and n counters. this input has an inverter biased in the linear region to allow use with ac coupled signals as low as 500 mv p?. for larger amplitude signals (standard cmos logic levels), dc coupling may be used. clk, data shift clock, serial data inputs (pins 9, 10) each low?o?igh transition of the clk shifts one bit of data into the on?hip shift registers. the last data bit entered determines which counter storage latch is activated; a logic 1 selects the reference counter latch and a logic 0 selects the a, n counter latch. the data entry format is as follows: enb latch enable input (pin 11) a logic high on this pin latches the data from the shift regis- ter into the reference divider or n, a latches depending on the control bit. the reference divider latches are activated if the control bit is at a logic high and the n, a latches are acti- vated if the control bit is at a logic low. a logic low on this pin allows the user to change the data in the shift registers without affecting the counters. enb is normally low and is pulsed high to transfer data to the latches. osc in , osc out reference oscillator input/output (pins 1, 2) these pins form an on?hip reference oscillator when con- nected to terminals of an external parallel resonant crystal. frequency setting capacitors of appropriate value must be con- nected from osc in to ground and osc out to ground. osc in may also serve as the input for an externally?enerated refer- ence signal. this signal is typically ac coupled to osc in , but for larger amplitude signals (standard cmos logic levels) dc coupling may also be used. in the external reference mode, no connection is required to osc out . lsb msb control first data bit into shift register r msb control n first data bit into shift register a lsb msb lsb 14?it shift register 7?it ? a counter v ml14515 8 block diagram r reference counter latch phase detector b phase detector a lock detect ld pd out f in osc in osc out enb 14 10 7?it s/r data clk 10 ref out a counter latch 14?it r counter 14 mc f r f v 1?it control s/r 10?it s/r n counter latch 10?it n counter control logic 7 7
www.lansdale.com page 22 of 35 # ml14515 8 output pins pd out phase detector a output (pin 5) this single?nded (three?tate) phase detector output pro- duces a loop?rror signal that is used with a loop filter to con- trol a vco. frequency f v > f r or f v leading: negative pulses frequency f v < f r or f v lagging: positive pulses frequency f v = f r and phase coincidence: high?mpedance state r, v phase detector b outputs (pins 16, 15) double?nded phase detector outputs. these outputs can be combined externally for a loop?rror signal. a single?nded output is also available for this purpose (see pd out ). if frequency f v is greater than f r or if the phase of f v is leading, then error information is provided by v pulsing low. r remains essentially high. if the frequency f v is less than f r or if the phase of f v is lagging, then error information is provided by r pulsing low. v remains essentially high. if the frequency of f v = f r and both are in phase, then both v and r remain high except for a small minimum time peri- od when both pulse low in phase. mc dual?odulus prescaler control output (pin 12) this output generates a signal by the on?hip control logic circuitry for controlling an external dual?odulus prescaler. the mc level is low at the beginning of a count cycle and remains low until the a counter has counted down from its programmed value. at this time, mc goes high and remains high until the n counter has counted the rest of the way down from its programmed value (n ?a additional counts since both n and a are counting down during the first por- tion of the cycle). mc is then set back low, the counters preset to their respective programmed values, and the above sequence repeated. this provides for a total programmable divide value (n t ) = n ?p + a where p and p + 1 represent the dual?odu- lus prescaler divide values respectively for high and low modu- lus control levels, n the number programmed into the n counter, and a the number programmed into the a counter. note that when a prescaler is needed, the dual?odulus ver- sion offers a distinct advantage. the dual?odulus prescaler allows a higher reference frequency at the phase detector input, increasing system performance capability, and simplifying the loop filter design. f r ,f v r counter output, n counter output (pins 13, 3) buffered, divided reference and fin frequency outputs. the f r and f v outputs are connected internally to the r and n counter outputs respectively, allowing the counters to be used independently, as well as monitoring the phase detector inputs. ld lock detector output (pin 7) this output is essentially at a high level when the loop is locked (f r , f v of same phase and frequency), and pulses low when loop is out of lock. ref out buffered reference oscillator output (pin 14) this output can be used as a second local oscillator, refer- ence oscillator to another frequency synthesizer, or as the sys- tem clock to a microprocessor controller. power supply v dd positive power supply (pin 4) the positive power supply potential. this pin may range from + 3 to + 9 v with respect to vss. v ss negative power supply (pin 6) the most negative supply potential. this pin is usually- ground. ml14515 8 lan s dale s emiconductor, inc.
www.lansdale.com page 23 of 35 issue a lan s dale s emiconductor, inc. ml1451xx ml14515x family characteri s tic s and de s cription s - continued maximum rating s * (voltages referenced to v ss ) s ymbol parameter value unit v dd dc supply voltage ?0.5 to + 10.0 v v in , v out input or output voltage (dc or transient) except sw1, sw2 ?0.5 to v dd + 0.5 v v out output voltage (dc or transient), sw1, sw2 (r pull?p = 4.7 k ) ?0.5 to + 15 v i in , i out input or output current (dc or transient), per pin 10 ma i dd , i ss supply current, v dd or v ss pins 30 ma p d power dissipation, per package? 500 mw t stg storage temperature ?65 to + 150 c t l lead temperature, 1 mm from case for 10 seconds 260 c * maximum ratings are those values b eyond which damage to the device may occur. functional operation should b e restricted to the limits in the electrical characteristics ta b les or pin descriptions section. ?power dissipation temperature derating: plastic dip: ?12 mw/ c from 65 to 8 5c sog package: ?7 mw/ c from 65 to 8 5c electrical characteri s tic s (voltages referenced to v ss ) v dd ?40 c 25 c 8 5c s ymbol parameter te s t condition v dd v min max min max min max unit v dd power supply voltage range 3 9 3 9 3 9 v i ss dynamic supply current f in = osc in = 10 mhz, 1 v p? ac coupled sine wave r = 12 8 , a = 32, n = 12 8 3 5 9 3.5 10 30 3 7.5 24 3 7.5 24 ma i ss quiescent supply current (not including pull?p current component) v in = v dd or v ss i out = 0 a 3 5 9 8 00 1200 1600 8 00 1200 1600 1600 2400 3200 a v in input voltage ?f in , osc in input ac coupled sine wave 500 500 500 mv p? v il lowlevel input v oltage ?f in , osc in v out 2.1 v input dc v out 3.5 v coupled v out 6.3 v s q uare wave 3 5 9 0 0 0 0 0 0 0 0 0 v v ih high?evel input voltage ?f in , osc in v out 0.9 v input dc v out 1.5 v coupled v out 2.7 v s q uare wave 3 5 9 3.0 5.0 9.0 3.0 5.0 9.0 3.0 5.0 9.0 v v il low?evel input voltage ?except f in , osc in 3 5 9 0.9 1.5 2.7 0.9 1.5 2.7 0.9 1.5 2.7 v v ih high?evel input voltage ?except f in , osc in 3 5 9 2.1 3.5 6.3 2.1 3.5 6.3 2.1 3.5 6.3 v i in input current (f in , osc in ) v in = v dd or v ss 9 2 50 2 25 2 22 a i il input leakage current (data, clk, enb without pull?ps) v in = v ss 9 ?0.3 ?0.1 ?1.0 a i ih input leakage current (all inputs except f in , osc in ) v in = v dd 9 0.3 0.1 1.0 a (continued) these devices contain protection circuitry to protect against damage due to high static voltages or electric fields. however, precau- tions must b e taken to avoid applications of any voltage higher than maximum rated voltages to these high?mpedance circuits. for proper operation, v in and v out should b e constrained to the range v ss (v in or v out ) v dd except for sw1 and sw2. sw1 and sw2 can b e tied through external resistors to voltages as high as 15 v, indepen- dent of the supply voltage. unused inputs must always b e tied to an appropriate logic voltage level (e.g., either v ss or v dd ), except for inputs with pull?p devices. unused outputs must b e left open.
www.lansdale.com page 24 of 35 issue a ml1451xx lan s dale s emiconductor, inc. dc electrical characteri s tic s (continued) v dd ?40 c 25 c 8 5c s ymbol parameter te s t condition v dd v min max min max min max unit i il pull?p current (all inputs with pull?ps) v in = v ss 9 ?20 ?400 ?20 ?200 ?20 ?170 a c in input capacitance 10 10 10 pf v ol low?evel output voltage ?osc out i out 0 a v in = v dd 3 5 9 0.9 1.5 2.7 0.9 1.5 2.7 0.9 1.5 2.7 v v oh high?evel output voltage ?osc out i out 0 a v in = v ss 3 5 9 2.1 3.5 6.3 2.1 3.5 6.3 2.1 3.5 6.3 v v ol low?evel output voltage ?other outputs i out 0 a 3 5 9 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 v v oh high?evel output voltage ?other outputs i out 0 a 3 5 9 2.95 4.95 8 .95 2.95 4.95 8 .95 2.95 4.95 8 .95 v v (br)dss drain?o?ource breakdown voltage sw1, sw2 r pull?p = 4.7 k 15 15 15 v i ol low?evel sinking current ?mc v out = 0.3 v v out = 0.4 v v out = 0.5 v 3 5 9 1.30 1.90 3. 8 0 1.10 1.70 3.30 0.66 1.0 8 2.10 ma i oh high?evel sourcing current ?mc v out = 2.7 v v out = 4.6 v v out = 8 .5 v 3 5 9 ?0.60 ?0.90 ?1.50 ?0.50 ?0.75 ?1.25 ?0.30 ?0.50 ?0. 8 0 ma i ol low?evel sinking current ?ld v out = 0.3 v v out = 0.4 v v out = 0.5 v 3 5 9 0.25 0.64 1.30 0.20 0.51 1.00 0.15 0.36 0.70 ma i oh high?evel sourcing current ?ld v out = 2.7 v v out = 4.6 v v out = 8 .5 v 3 5 9 ?0.25 ?0.64 ?1.30 ?0.20 ?0.51 ?1.00 ?0.15 ?0.36 ?0.70 ma i ol low?evel sinking current ?sw1, sw2 v out = 0.3 v v out = 0.4 v v out = 0.5 v 3 5 9 0. 8 0 1.50 3.50 0.4 8 0.90 2.10 0.24 0.45 1.05 ma i ol low?evel sinking current ?other outputs v out = 0.3 v v out = 0.4 v v out = 0.5 v 3 5 9 0.44 0.64 1.30 0.35 0.51 1.00 0.22 0.36 0.70 ma i oh high?evel sourcing current ?other outputs v out = 2.7 v v out = 4.6 v v out = 8 .5 v 3 5 9 ?0.44 ?0.64 ?1.30 ?0.35 ?0.51 ?1.00 ?0.22 ?0.36 ?0.70 ma i oz output leakage current pd out v out = v dd or v ss output in off state 9 0.3 0.1 1.0 a i oz output leakage current sw1, sw2 v out = v dd or v ss output in off state 9 0.3 0.1 3.0 a c out output capacitance pd out pd out ?three?tate 10 10 10 pf
www.lansdale.com page 25 of 35 issue a lan s dale s emiconductor, inc. ml1451xx ac electrical characteri s tic s (c l = 50 pf, input t r = t f = 10 ns) s ymbol parameter v dd v guaranteed limit 25 5 c guaranteed limit ?40 to 8 5 c unit t plh , t phl maximum propagation delay, f in to mc (figures 1 and 4) 3 5 9 110 60 35 120 70 40 ns t phl maximum propagation delay, enb to sw1, sw2 (figures 1 and 5) 3 5 9 160 8 0 50 1 8 0 95 60 ns t w output pulse width, r , v , and ld with f r in phase with f v (figures 2 and 4) 3 5 9 25 to 200 20 to 100 10 to 70 25 to 260 20 to 125 10 to 8 0 ns t tlh maximum output transition time, mc (figures 3 and 4) 3 5 9 115 60 40 115 75 60 ns t thl maximum output transition time, mc (figures 3 and 4) 3 5 9 60 34 30 70 45 3 8 ns t tlh , t thl maximum output transition time, ld (figures 3 and 4) 3 5 9 1 8 0 90 70 200 120 90 ns t tlh , t thl maximum output transition time, other outputs (figures 3 and 4) 3 5 9 160 8 0 60 175 100 65 ns s witching waveform s test point device under test c l * * includes all pro b e and fixture capacitance. test point device under test c l * * includes all pro b e and fixture capacitance. v dd 15 k t tlh 90% 10% t thl any output fi g ure 1. fi g ure 2. 50% output 50% input t plh v ss v dd t phl 50% r , v , ld* *f r in phase with f v . t w output output fi g ure 3 . fi g ure 4. te s t circuit fi g ure 5. te s t circuit
www.lansdale.com page 26 of 35 issue a ml1451xx lan s dale s emiconductor, inc. timing requirement s (input t r = t f = 10 ns unless otherwise indicated) s ymbol parameter v dd v guaranteed limit 25 c guaranteed limit ?40 to 8 5c unit f clk serial data clock fre q uency, assuming 25% duty cycle note: refer to clk t w(h) b elow (figure 6) 3 5 9 dc to 5.0 dc to 7.1 dc to 10 dc to 3.5 dc to 7.1 dc to 10 mhz t su minimum setup time, data to clk (figure 7) 3 5 9 30 20 1 8 30 20 1 8 ns t h minimum hold time, clk to data (figure 7) 3 5 9 40 20 15 40 20 15 ns t su minimum setup time, clk to enb (figure 7) 3 5 9 70 32 25 70 32 25 ns t rec minimum recovery time, enb to clk (figure 7) 3 5 9 5 10 20 5 10 20 ns t w(h) minimum pulse width, clk and enb (figure 6) 3 5 9 50 35 25 70 35 25 ns t r , t f maximum input rise and fall times ?any input (figure 8 ) 3 5 9 5 4 2 5 4 2 s s witching waveform s fi g ure 6. fi g ure 7. v ss v dd 50% 50% last clk previous data latched first clk enb clk data 50% ?v dd v ss ?v dd v ss ?v dd v ss t su t su t rec t h 50% clk, enb t w(h) ?v dd v ss 4 f clk 1 * *assumes 25% duty cycle. t r 90% 10% t f any output fi g ure 8 .
www.lansdale.com page 27 of 35 issue a lan s dale s emiconductor, inc. ml1451xx frequency characteri s tic s (voltages references to v ss , c l = 50 pf, input t r = t f =10 ns unless otherwise indicated) v dd ?40 c 25 c 8 5c s ymbol parameter te s t condition v dd v min max min max min max unit f i input fre q uency (f in , osc in ) r 8 , a 0, n 8 v in = 500 mv p? ac coupled sine wave 3 5 9 6 15 15 6 15 15 6 15 15 mhz r 8 , a 0, n 8 v in = 1 v p? ac coupled sine wave 3 5 9 12 22 25 12 20 22 7 20 22 mhz r 8 , a 0, n 8 v in = v dd to v ss dc coupled s q uare wave 3 5 9 13 25 25 12 22 25 8 22 25 mhz note: usually, the pll's propagation delay from f in to mc plus the setup time of the prescaler determines the upper fre q uency limit of the system. the upper fre q uency limit is found with the following formula: f = p / (t p + t set ) where f is the upper fre q uency in hz, p is the lower of the dual modulus prescaler ratios, t p is the f in to mc propagation delay in seconds, and t set is the prescaler setup time in seconds. for example, with a 5 v supply, the f in to mc delay is 70 ns. if the mc1202 8 a prescaler is used, the setup time is 16 ns. thus, if the 64/65 ratio is utilized, the upper fre q uency limit is f = p / (t p + t set ) = 64/(70 + 16) = 744 mhz. v h = high voltage level. v l = low voltage level. * at this point, when b oth f r and f v are in phase, the output is forced to near mid?upply. note: the pd out generates error pulses during out?f?ock conditions. when locked in phase and fre q uency the output is high and the voltage at this pin is determined b y the low?ass filter capacitor. f r reference osc r f v feedback (f in n) pd out r v ld * v h v l v h v l v h high impedance v h v l v h v l v h v l v l fi g ure 9. pha s e detector/lock detector output waveform s
www.lansdale.com page 2 8 of 35 issue a ml1451xx lan s dale s emiconductor, inc. de s ign con s ideration s pha s e?ocked loop ?low?a ss filter de s ign c) _ + a c r 2 c vco c vco r 2 b) a) c vco pd out pd out r v pd out r v r 1 r 1 r 1 r 1 r 2 note: sometimes r 1 is split into two series resistors, each r 1 2. a capacitor c c is then placed from the midpoint to ground to further filter v and r . the value of c c should b e such that the corner fre q uency of this network does not significantly affect n . the r and v outputs swing rail?o?ail. therefore, the user should b e careful not to exceed the common mode input range of the op amp used in the com b iner/loop filter. definitions: n = total division ratio in feed b ack loop k (phase detector gain) = v dd / 4 for pd out k (phase detector gain) = v dd /2 for v and r k vco (vco gain) = 2 ? f vco ? v vco for a typical design w n (natural fre q uency) 2 fr 10 (at phase detector input). damping factor: ? 1 recommended reading: gardner, floyd m., phaselock techni q ues (second edition). new york, wiley?nterscience, 1979. manassewitsch, vadim, fre q uency synthesizers: theory and design (second edition). new york, wiley?nterscience, 19 8 0. blanchard, alain, phase locked loops: application to coherent receiver design. new york, wiley?nterscience, 1976. egan, william f., fre q uency synthesis b y phase lock. new york, wiley?nterscience, 19 8 1. rohde, ulrich l., digital pll fre q uency synthesizers theory and design. englewood cliffs, nj, prentice?all, 19 8 3. berlin, howard m., design of phase locked loop circuits, with experiments. indianapolis, howard w. sams and co., 197 8 . kinley, harold, the pll synthesizer cook b ook. blue ridge summit, pa, ta b books, 19 8 0. an535, phase?ocked loop design fundamentals, motorola semiconductor products, inc., 1970. ar254, phase?ocked loop design articles, motorola semiconductor products, inc., reprinted with permission from electronic design, 19 8 7. r v f(s) = assuming gain a is very large, then: f(s) = = n = nr 1 c r 1 sc + 1 n = = n r 2 c 2 r 2 sc + 1 r 1 sc 1 n n 2k k vco f(s) = = n = (r () 1 +r 2 )sc + 1 r 2 sc + 1 nc(r 1 + r 2 ) r 2 c+ n k k vco k k vco ncr 1 0.5 n k k vco k k vco
www.lansdale.com page 29 of 35 issue a ml1451xx lan s dale s emiconductor, inc. crystal oscillator considerations the following options may be considered to provide a refer- ence frequency to motorola's or lansdales cmos frequency synthesizers. use of a hybrid crystal oscillator commercially available temperature?ompensated crystal oscillators (tcxos) or crystal?ontrolled data clock oscilla- tors provide very stable reference frequencies. an oscillator capable of sinking and sourcing 50 a at cmos logic levels may be direct or dc coupled to osc in . in general, the highest frequency capability is obtained utilizing a direct?oupled square wave having a rail?o?ail (v dd to v ss ) voltage swing. if the oscillator does not have cmos logic levels on the outputs, capacitive or ac coupling to osc in may be used. osc out , an unbuffered output, should be left floating. for additional information about tcxos and data clock oscillators, please consult the latest version of the eem elec- tronic engineers master catalog, the gold book, or similar publications. design an off?hip reference the user may design an off?hip crystal oscillator using ics specifically developed for crystal oscillator applications, such as the ml12061 mecl device. the reference signal from the mecl device is ac coupled to osc in . for large amplitude signals (standard cmos logic levels), dc coupling is used. osc out , an unbuffered output, should be left floating. in gen- eral, the highest frequency capability is obtained with a di- rect?oupled square wave having rail?o?ail voltage swing. use of the on?hip oscillator circuitry the on?hip amplifier (a digital inverter) along with an ap- propriate crystal may be used to provide a reference source fre- quency. a fundamental mode crystal, parallel resonant at the desired operating frequency, should be connected as shown in figure 10. for v dd = 5.0 v, the crystal should be specified for a loading capacitance, c l , which does not exceed 32 pf for frequencies to approximately 8.0 mhz, 20 pf for frequencies in the area of 8.0 to 15 mhz, and 10 pf for higher frequencies. these are guidelines that provide a reasonable compromise between ic capacitance, drive capability, swamping variations in stray and ic input/output capacitance, and realistic c l values. the shunt load capacitance, c l , presented across the crystal can be estimated to be: the oscillator can be ?rimmed?on?requency by making a portion or all of c1 variable. the crystal and associated com- ponents must be located as close as possible to the osc in and osc out pins to minimize distortion, stray capacitance, stray inductance, and startup stabilization time. in some cases, stray capacitance should be added to the value for c in and c out . power is dissipated in the effective series resistance of the crystal, re, in figure 12. the drive level specified by the crys- tal manufacturer is the maximum stress that a crystal can with- stand without damage or excessive shift in frequency. r1 in figure 10 limits the drive level. the use of r1 may not be nec- essary in some cases (i.e., r1 = 0 ). to verify that the maximum dc supply voltage does not overdrive the crystal, monitor the output frequency as a func- tion of voltage at osc out . (care should be taken to minimize loading.) the frequency should increase very slightly as the dc supply voltage is increased. an overdriven crystal will decrease in frequency or become unstable with an increase in supply voltage. the operating supply voltage must be reduced or r1 must be increased in value if the overdriven condition exists. the user should note that the oscillator start?p time is proportional to the value of r1. through the process of supplying crystals for use with cmos inverters, many crystal manufacturers have developed expertise in cmos oscillator design with crystals. discussions with such manufacturers can prove very helpful (see table 1). fi g ure 10. pierce cry s tal o s cillator circuit r1* c2 c1 frequency synthesizer osc out osc in * may b e deleted in certain cases. see text. r f c l = c in c out c in + c out + c a + c o + c1 c2 c1 + c2 where c in = 5 pf (see figure 11) c out = 6 pf (see figure 11) c a = 1 pf (see figure 11) c o = the crystal's holder capacitance (see figure 12) c1 and c2 = external capacitors (see figure 10) fi g ure 11. para s itic capacitance s of the amplifier c in c out c a fi g ure 12. equivalent cry s tal network s note: values are supplied b y crystal manufacturer (parallel resonant crystal). 2 1 2 1 2 1 r s l s c s r e x e c o
www.lansdale.com page 30 of 35 issue a ml1451xx lan s dale s emiconductor, inc. recommended reading technical note tn?4, statek corp. technical note tn?, statek corp. e. hafner, ?he piezoelectric crystal unit ?definitions and method of measurement? proc. ieee, vol. 57, no. 2 feb.,1969. d. kemper, l. rosine, ?uartz crystals for frequencycontrol? electro?echnology, june, 1969. p. j. ottowitz, a guide to crystal selection? electronic design, may, 1966. dual?odulus prescaling overview the technique of dual?odulus prescaling is well estab- lished as a method of achieving high performance frequency synthesizer operation at high frequencies. basically, the approach allows relatively low?requency programmable coun- ters to be used as high?requency programmable counters with speed capability of several hundred mhz. this is possible with out the sacrifice in system resolution and performance that results if a fixed (single?odulus) divider is used for the prescaler. in dual?odulus prescaling, the lower speed counters must be uniquely configured. special control logic is necessary to select the divide value p or p + 1 in the prescaler for the required amount of time (see modulus control definition). lansdale's dual?odulus frequency synthesizers contain this feature and can be used with a variety of dual?odulus- prescalers to allow speed, complexity and cost to be tailored to the system requirements. prescalers having p, p + 1 divide val- ues in the range of 3/? to ?28/ 129 can be controlled by most lansdale frequency synthesizers. several dualmodulus prescaler approaches suitable for use with the mc145152 (motorola), ml145156, or ml145158 are: design guidelines the system total divide value, n total (n t ) will be dictated by the application: n is the number programmed into the n counter, a is the number programmed into the a counter, p and p + 1 are the two selectable divide ratios available in the dual?odulus prescalers. to have a range of n t values in sequence, the a counter is programmed from zero through p ?1 for a par- ticular value n in the n counter. n is then incremented to n + 1 and the a is sequenced from 0 through p ?1 again. there are minimum and maximum values that can be achieved for n t . these values are a function of p and the size of the n and a counters. the constraint n a always applies. if a max = p ?1, then n min p ?1. then n t min = (p ?1) p + a or (p ?1) p since a is free to assume the value of 0. nt max = n max ?p + a max to maximize system frequency capability, the dual?odulus prescaler output must go from low to high after each group of p or p + 1 input cycles. the prescaler should divide by p when its modulus control line is high and by p + 1 when its mc is low. for the maximum frequency into the prescaler (f vcomax ), the value used for p must be large enough such that: 1.f vco max divided by p may not exceed the frequency capability of f in (input to the n and a counters). 2.the period of f vco divided by p must be greater than the sum of the times: a. propagation delay through the dual?odulus prescaler. b. prescaler setup or release time relative to its mc signal. c. propagation time from f in to the mc output for the frequency synthesizer device. a sometimes useful simplification in the programming code can be achieved by choosing the values for p of 8, 16, 32, or 64. for these cases, the desired value of n t results when n t in binary is used as the program code to the n and a coun- ters treated in the following manner: 1.assume the ? counter contains ??bits where 2 a p. 2.always program all higher order ? counter bits above ??to 0. table 1. partial li s t of cry s tal manufacturer s united states crystal corp. crystek crystal statek corp. fox electronics note: lansdale and motorola do not recommend one supplier over another and in no way suggests that this is a complete listing of crystal manufacturers. ml12009 ml12011 ml12013 ml12015 ml12016 ml12017 ml1201 8 mc1202 8 a ml12052 ml12054a 5/ 6 8 / 9 10/ 11 32/ 33 40/ 41 64/ 65 12 8 / 129 32/33 or 64/65 64/65 or 12 8 /129 64/65 or 12 8 /129 440 mhz 500 mhz 500 mhz 225 mhz 225 mhz 225 mhz 520 mhz 1.1 ghz mc12034 ?2/33 or ?4/65 ?27/12 8 or ?55/256 2.0 ghz mc1203 8 1.1 ghz 1.1 ghz 2.0 ghz n t = fre q uency into the prescaler fre q uency into the phase detector = n p + a
www.lansdale.com page 31 of 35 issue a ml1451xx lan s dale s emiconductor, inc. 3. assume the ? counter and the ? counter (with all the higher order bits above ??ignored) combined into a single binary counter of n + a bits in length (n = number of divider stages in the ? counter). the msb of this ?ypothetical counter is to correspond to the msb of n and the lsb is to correspond to the lsb of a. the system divide value, n t , now results when the value of n t in binary is used to program the ?ew?n + a bit counter. by using the two devices, several dual?odulus values are achievable (shown in figure 13). mc device b device a device b ml12009 ml12011 ml12013 device a mc10131 mc1013 8 20/ 21 50/ 51 32/ 33 8 0/ 8 1 40/ 41 100/ 101 note: ml12009, ml12011, and ml12013 are pin e q uivalent. ml12015, ml12016, and ml12017 are pin e q uivalent. fi g ure 1 3 . dual?odulu s value s
www.lansdale.com page 32 of 35 issue a ml1451xx lan s dale s emiconductor, inc. outline dimen s ion s p dip 16 = ep pla s tic dip ca s e 64 8 ? 8 (ml145157ep, ml14515 8 ep) notes: 1. dimensioning and tolerancing per ansi y14.5m, 19 8 2. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. ? b f c s h g d j l m 16 pl s eating 9 16 k plane ? m a m 0.25 (0.010) t dim min max min max millimeter s inche s a 0.740 0.770 1 8 . 8 0 19.55 b 0.250 0.270 6.35 6. 8 5 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.00 8 0.015 0.21 0.3 8 k 0.110 0.130 2. 8 0 3.30 l 0.295 0.305 7.50 7.74 m 0? 10? 0? 10? s 0.020 0.040 0.51 1.01 p dip 1 8 = vp pla s tic dip ca s e 707?2 (ml145155vp) min min max max millimeter s inche s dim 22.22 6.10 3.56 0.36 1.27 1.02 0.20 2.92 23.24 6.60 4.57 0.56 1.7 8 1.52 0.30 3.43 0 0.51 0. 8 75 0.240 0.140 0.014 0.050 0.040 0.00 8 0.115 0.915 0.260 0.1 8 0 0.022 0.070 0.060 0.012 0.135 15 1.02 2.54 bsc 7.62 bsc 0.100 bsc 0.300 bsc 0 0.020 15 0.040 a b c d f g h j k l m n notes: 1. positional tolerance of leads (d), shall be within 0.25 (0.010) at maximum material condition, in relation to seating plane and each other. 2. dimension l to center of leads when formed parallel. 3. dimension b does not include mold flash. 10 1 8 b a h f g d s eating plane n k m j l c
www.lansdale.com page 33 of 35 issue a ml1451xx lan s dale s emiconductor, inc. p dip 20 = rp pla s tic dip ca s e 7 38 ? 3 (ML145156RP) 1.070 0.260 0.1 8 0 0.022 0.070 0.015 0.140 15 0.040 1.010 0.240 0.150 0.015 0.050 0.00 8 0.110 0 0.020 25.66 6.10 3. 8 1 0.39 1.27 0.21 2. 8 0 0 0.51 27.17 6.60 4.57 0.55 1.77 0.3 8 3.55 15 1.01 0.050 bsc 0.100 bsc 0.300 bsc 1.27 bsc 2.54 bsc 7.62 bsc min min max max inche s millimeter s dim a b c d e f g j k l m n notes: 1. dimensioning and tolerancing per ansi y14.5m, 19 8 2. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimension b does not include mold flash. -a- c k n e gf d 20 pl j 20 pl l m -t- s eating plane 1 10 11 20 0.25 (0.010) t a m m 0.25 (0.010) t b m m b s og 20 = -6p s og package ca s e 751d?4 (mc145155-6p, mc145156-6p) notes: 1. dimensioning and tolerancing per ansi y14.5m, 19 8 2. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.150 (0.006) per side. 5. dimension d does not include dambar protrusion. allow able dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. ? ? 20 1 11 10 s a m 0.010 (0.25) b s t d 20x m b m 0.010 (0.25) p 10x j f g 1 8 x k c ? s eating plane m r x 45 dim min max min max inche s millimeter s a 12.65 12.95 0.499 0.510 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0? 7? 0? 7? p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 outline dimen s ion s
www.lansdale.com page 34 of 35 issue a ml1451xx lan s dale s emiconductor, inc. p dip 28 = yp outline dimensions plastic dip case 710?2 (ml145151yp, ml145152yp) 0.100 b s c 0.600 b s c 2.54 b s c 15.24 b s c min min max max millimeters inches dim 3 6.45 1 3 .72 3 .94 0. 3 6 1.02 1.65 0.20 2.92 0 0.51 3 7.21 14.22 5.08 0.56 1.52 2.16 0. 3 8 3 .4 3 15 1.02 1.4 3 5 0.540 0.155 0.014 0.040 0.065 0.008 0.115 0 0.020 1.465 0.560 0.200 0.022 0.060 0.085 0.015 0.1 3 5 15 0.040 a b c d f g h j k l m n note s : 1. po s itional tolerance of lead s (d), s hall be within 0.25mm (0.010) at maximum material condition, in relation to s eating plane and each other. 2. dimen s ion l to center of lead s when formed parallel. 3 . dimen s ion b doe s not include mold fla s h. 1 14 15 28 b a c n k m j d seating plane f hg l so 28w = -6p sog package case 751f?4 (ml145151-6p, ml145152?p) min min max max millimeters inches dim a b c d f g j k m p r 17.80 7.40 2. 3 5 0. 3 5 0.41 0.2 3 0.1 3 0 10.05 0.25 18.05 7.60 2.65 0.49 0.90 0. 3 2 0.29 8 10.55 0.75 0.701 0.292 0.09 3 0.014 0.016 0.009 0.005 0 0. 3 95 0.010 0.711 0.299 0.104 0.019 0.0 3 5 0.01 3 0.011 8 0.415 0.029 1.27 b s c 0.050 b s c note s : 1. dimen s ioning and tolerancing per an s i y14.5m, 1982. 2. controlling dimen s ion: millimeter. 3 . dimen s ion a and b do not include mold protru s ion. 4. maximum mold protru s ion 0.15 (0.006) per s ide. 5. dimen s ion d doe s not include dambar protru s ion. allowable dambar protru s ion s hall be 0.1 3 (0.005) total in exce ss of d dimen s ion at maximum material condition. -a- -b- 1 14 15 28 -t- c seating plane 0.010 (0.25) b m m m j -t- k 26x g 28x d 14x p r x 45 f 0.010 (0.25) t a b m s s
www.lansdale.com page 35 of 35 issue a lansdale semiconductor reserves the right to make changes without further notice to any products herein to improve relia b ili- ty, function or design. lansdale does not assume any lia b ility arising out of the application or use of any product or circuit descri b ed herein; neither does it convey any license under its patent rights nor the rights of others. typical parameters which may b e provided in lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. all operating parameters, including typicals must b e validated for each customer application b y the customers technical experts. lansdale semiconductor is a registered trademark of lansdale semiconductor, inc. ml1451xx lan s dale s emiconductor, inc. s og 20 = -5p s og package ca s e 751g?2 (ml145157-5p, ml14515 8 -5p) dim min max min max inche s millimeter s a 10.15 10.45 0.400 0.411 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7? 7? 0? p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 m b m 0.010 (0.25) notes: 1. dimensioning and tolerancing per ansi y14.5m, 19 8 2. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allow able dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. ? ? p 8 x g 14x d 16x s eating plane ? s a m 0.010 (0.25) b s t 16 9 8 1 f j r x 45 m c k outline dimen s ion s

▲Up To Search▲

Price & Availability of ML145156RP

	To Download ML145156RP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .